iT邦幫忙

2022 iThome 鐵人賽
DAY 23
0
Software Development

超簡單的 Verilog 入門講解系列 第 23 篇

[Day 23] Verilog E-1 難度丁 P2海域的消血3 - Rs232訊號協議 讀取第一個資料 b0 ( 設計輸出2 )

14th鐵人賽
432 瀏覽

  • 分享至 

  • xImage
    •  

回到 Day21 的程式碼


module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;


reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin

   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0ㄤ
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

我們加入第2狀態


module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;


reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin

   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0ㄤ
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    
    2:
    begin
    
    
    end
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

那第2狀態是甚麼呢?
其實有兩個方法

  1. 進入 Start 的沒做任何事情，然後再進到第3狀態再去收 bin0 的值

移動 0.5 bin 從 Start 到中間

https://ithelp.ithome.com.tw/upload/images/20221006/20135862QtR038SeKE.png

  1. 或是直接進去 bin0 收值

移動 1.5 bin 直接進去 bin0

https://ithelp.ithome.com.tw/upload/images/20221006/201358626bcvJNTWJq.png

麻~ 最好的解當然是2，我就寫1，2留給你們自己練習

收一個 0.5 Bin的長度，如果超過 Bin 長度就跳到 State 3

https://ithelp.ithome.com.tw/upload/images/20221006/20135862IWSnzkVQ7r.png

一半為 288/2 =144
從0開始數所以減1 = 143

 2:
    begin
         if(Count_clk >= 143 ) begin
    
                Count_clk<=0;
                State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end

然後再將 State 3 也一樣移動 1 bin 到數據中間

https://ithelp.ithome.com.tw/upload/images/20221006/2013586283v7HjtII7.png

 2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end

將這段加入程式碼


module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;


reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin

   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0ㄤ
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    // 將這段加入程式碼
    2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

進入 b0 要做甚麼呢 紀錄數據阿，紀錄再 Output的 第0位

所以 Out1 是個 reg


reg[7:0] Out1;

設定為 Reg 就要馬上給他初始化


module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;
// 所以 Out1 是個 reg
reg[7:0] Out1;

reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin
   //設定為 Reg 就要馬上給他初始化
   Out1<=0;
   
   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0ㄤ
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    // 將這段加入程式碼
    2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

最後將 讀到的 Data 付值到 Out1的第0位

3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               // 讀到的 Data  付值到 Out1的第0位
               Out1[0] <=Data;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end

加到程式碼吧


module Rs232_test1(Data1,clk,reset1,Out1,En_out);
input Data1,reset1 ,clk;
output[7:0] Out1;
output En_out;

reg[7:0] State1;


reg[7:0] Count_clk;
reg[7:0] Count_bin;
// 所以 Out1 是個 reg
reg[7:0] Out1;

reg[7:0] Data_Previous1;


always@(negedge reset1 or posedge clk)
begin

if( ~reset1) begin
   //設定為 Reg 就要馬上給他初始化
   Out1<=0;
   
   Count_clk<=0;
   Count_bin<=0;
   Data_Previous1<=0ㄤ
   State1 <=0;
end
else begin
    
    Data_Previous1 <= Data1;
    
    case (State1)
    0:
    begin
      
        if(Count_clk >= 287 ) begin
        
            Count_clk<=0;
        
        end
        
        else begin
        
            Count_clk <= Count_clk + 1;
        
        end
        
        if(Count_clk == 0 )begin
            if(Data1==1)begin
                Count_bin <= Count_bin+1;
            end
            else begin
                Count_bin <= 0;
            end
        end
        
        if(Count_bin== 15 )begin
                State1 <= 1;
        end
        
        
    end
    1:
    begin
          if(~Data_Previous1 & Data1 ) begin

            State1 <= 2;

          end
    end  
    // 將這段加入程式碼
    2:
    begin
         if(Count_clk >= 143 ) begin
    
               Count_clk<=0;
               State1 <= 3;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end
3:
    begin  
        if(Count_clk >= 287 ) begin
    
               Count_clk<=0;
               // 讀到的 Data  付值到 Out1的第0位
               Out1[0] <=Data;
               State1 <= 4;
        end
        else begin
                Count_clk<=Count_clk+1;
    
        end
    end  
    default:
    begin
          
          
    end
       
    endcase
    
end

end

endmodule

那我們走到了
https://ithelp.ithome.com.tw/upload/images/20221006/20135862tQCXwHh1md.png


上一篇
[Day 22] Verilog E-1 難度丁 P2海域的消血2 - Rs232訊號協議 Data delay 再講一次 ( 設計輸出1.5 )
下一篇
[Day 24] Verilog E-1 難度丁 P2海域的消血4 - Rs232訊號協議 讀取第一個資料 b0~b7 ( 設計輸出3 )
系列文
超簡單的 Verilog 入門講解 共 30 篇
  1. 26
    [Day 26] Verilog E-1 難度丁 P2海域的斬殺1 - Rs232訊號協議 TB設計(TB的初始框架)
  2. 27
    [Day 27] Verilog E-1 難度丁 P2海域的斬殺2 - Rs232訊號協議 TB設計2(計算輸入資料的 clk數量)
  3. 28
    [Day 28] Verilog E-1 難度丁 P2海域的斬殺3 - Rs232訊號協議 TB設計3(初始化輸入數據)
  4. 29
    [Day 29] Verilog E-1 難度丁 P2海域的斬殺4 - Rs232訊號協議 TB設計4(設計右移)
  5. 30
    [Day 30] Verilog E-1 難度丁 - P2 結尾
完整目錄
圖片
  直播研討會
圖片
{{ item.channelVendor }} {{ item.webinarstarted }} |
{{ formatDate(item.duration) }}
直播中

尚未有邦友留言

立即登入留言
iThome鐵人賽
參賽組數
1064 組
團體組數
40 組
累計文章數
22201 篇
完賽人數
602 人
iT+看影片追技術 看影片追技術 看更多
熱門tag 看更多
15th鐵人賽 16th鐵人賽 13th鐵人賽 14th鐵人賽 12th鐵人賽 11th鐵人賽 鐵人賽 2019鐵人賽 javascript 2018鐵人賽 python 2017鐵人賽 windows php c# windows server linux css react vue.js
熱門問題
熱門回答
熱門文章
IT邦幫忙